The present application relates to high-voltage semiconductor devices, and more particularly to termination regions for high-voltage semiconductor devices.
Note that the points discussed below may reflect the hindsight gained from the disclosed inventions, and are not necessarily admitted to be prior art.
The design of the edge termination structure of a high voltage semiconductor device is crucial to its long-term operation. A termination structure that has been designed to operate in a given set of conditions may exhibit a considerable reduction in voltage handling ability in the presence of unwanted positive or negative charge that is at or near the surface of the termination structure.
Trajkovic et al. investigated this effect in “The effect of static and dynamic parasitic charge in the termination region of high voltage devices and possible solutions,” The 12th International Symposium on Power Semiconductor Devices and ICs, Proceedings, pp. 263-266, May 22-25, 2000, IEEE, which is hereby incorporated by reference. In Trajkovic's simulations, which are reproduced here as FIGS. 9A, 9B, and 9C, when no charge was present in the oxide layer above a device, the breakdown voltage of the device was Vbr=1600 V, as in FIG. 9A. When positive charge was present in the oxide layer, as in FIG. 9B, the breakdown voltage of the device was Vbr=870 V. When negative charge was present in the oxide layer, as in FIG. 9C, the breakdown voltage of the device was Vbr=980 V.
Commonly-owned and co-pending application Ser. No. 14/313,960, which is hereby incorporated by reference, taught novel bidirectional bipolar transistors known as B-TRANs. B-TRANs are three-layer four-terminal vertically-symmetric bidirectional bipolar transistors having at least two leads on each surface. One junction on each surface of the B-TRAN acts as an emitter, and the corresponding junction on the opposite surface acts as a collector; which side is the emitter depends on the polarity of the applied voltage.
The present application teaches, among other innovations, power semiconductor devices having reduced sensitivity to surface charge.
The present application also teaches, among other innovations, methods of operating power semiconductor devices to reduce sensitivity to surface charge.
The above innovations are implemented, in various disclosed embodiments, by replicating portions of carrier-emission structures from the active area(s) of a device in one or more field-limiting rings. The field-limiting rings can also include field plates which extend out over, and are capacitively coupled to, an adjacent annulus of dielectric. In a preferred and particularly advantageous class of embodiments, the active device is a vertically symmetric four-terminal two-surface bipolar transistor, in which current is turned on, in one direction, by driving a gate terminal near the carrier emission structure which will operate, in that direction of current, as emitter.